As silicon technology advances to ultra-large scale integration (ULSI), the devices on silicon wafers shrink to sub-micron dimension and the circuit density increases to several million transistors per die. In order to accomplish this high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges, of various features.
One manufacturing technique for improving the circuit density on a silicon semiconductor die involves roughening a surface of the semiconductor wafer during manufacture thereof. There are various reasons for providing a roughened surface on a semiconductor wafer or die. Some examples are: (1) to provide additional surface area within the confines of a given volume, i.e., to increase the capacitance of a DRAM storage cell; (2) to provide better adhesion for adjacent or connecting insulators or conductors; (3) to reduce reflective notching in the photolithography process, due to the reabsorption of incident light by adjacent surface irregularities; and (4) to improve the efficiency of solar cells by providing a light entry surface having surface irregularities for absorbing the incident light.
In the past, roughening of the semiconductor surface has been accomplished by mechanical abrasion or sanding. Mechanical roughening is typically a messy procedure which may introduce contaminants into the manufacturing process. The presence of particulate contaminants may, for example, produce patterning errors during a photopatterning process.
An exemplary mechanical process for roughening a semiconductor surface is disclosed in U.S. Pat. No. 4,917,752 to Jensen. The method disclosed in Jensen involves "lapping" the back side of a silicon sphere to provide a roughened surface for better adhesion to an aluminum foil. The aluminum foil is then preheated and impact pressed to the roughened sphere.
Other prior art patents have disclosed methods of roughening a semiconductor surface without mechanical abrasion. An example of a method for treating a semiconductor substrate to provide a roughened surface, without mechanical abrasion, is disclosed in U.S. Pat. No. 4,294,651 to Ohmura. In Ohmura, the back side of a substrate is etched with a mixture of a fluorine compound, an oxidizing agent, and an alkali to produce a roughened surface. If an even rougher surface is desired, the substrate is pre-etched with a mixture of a fluorine compound and a manganese-containing oxidizing agent. In this case, the purpose of the roughening is to promote adhesion to an adjacent metal layer.
A problem with such prior art processes is that the chemical etchants used and the etching technique may degrade the electrical characteristics of the semiconductor devices formed on the silicon substrate. Additionally, the process steps may be difficult to accurately control in a manufacturing environment.
A third patent, U.S. Pat. No. 4,663,188 to Kane, discloses a process of depositing a light transmissive electrical contact, i.e., SnO.sub.2, having a textured surface, on top of a clear substrate to form a photo detector electrical contact. The roughened or textured surface is accomplished by a chemical vapor deposition process. The technique disclosed in Kane is not applicable to most semiconductor manufacturing process.
The present invention is directed to a method for roughening a silicon or polysilicon semiconductor surface in which there is no mechanical abrasion of the surface. The method of the invention contemplates the use of chemical etchants and techniques that are compatible with manufacturing operations and that do not degrade the electrical characteristics of the finished semiconductor devices.